exwein
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Init RDT
VER: RDT_S02027,Jul 27 2018,11:16:26,8215,60
[vGDP_Set_Nand_Timing],1
nifc_timing_set.config 2222
nops_tmr_cnfg0.bits.nops_tmr_un0 0d05
nops_tmr_cnfg0.bits.nops_tmr_un1 014d
nops_tmr_cnfg1.bits.nops_tmr_un2 0021
nops_tmr_cnfg1.bits.nops_tmr_un3 0000
nops_rty_cnfg0.bits.nops_rty_th0 00ff
nops_rty_cnfg0.bits.nops_rty_th1 00ff
nops_rty_cnfg0.bits.nops_rty_th2 00ff
nops_rty_cnfg0.bits.nops_rty_th3 00ff
Type 33
Pll 3aa97
gbRow_Block_Shift a
pParam->bFlashVendor 4
pParam->bFlashType 3
pParam->wBlocks 2944
pParam->wExtend_blocks 0
pParam->wPages 3072
pParam->wPageSize 16
pParam->bLuns 1
pParam->wLunOffsetUnit 0
pParam->bPlanes 4
pParam->bMode 8
pParam->bLdpcMode 0
pParam->bMaxChans 2
pParam->bMaxBanks 1
pParam->wDefectRatio 72
bNandClass 7
pParam->bCwFormat[]:{3,0,0,1,1,0,0}
pParam->bFwCh[]:{0,1}
pParam->bFwBank[]:{0}
gbBlock_Shift a
gbRow_Block_Shift a
gbPage_Shift c
gbRow_Page_Shift c
gbLun_Shift 0
gbPlane_Shift 2
gbStpu_Shift 7
gbCh_Shift 1
gbCe_Shift 0
gbCe_Num 1
CH#0 BK#0 Flash ID = 0x89 0xD4 0xC 0x32 0xAA 0x0 0x0
CH#1 BK#0 Flash ID = 0x89 0xD4 0xC 0x32 0xAA 0x0 0x0
Update GDP
gdp_media.erase=58 12
gdp_media.prog=8c 18
gdp_media.read=186 39
Full CH Map = 0 1 FF FF
Full CE Map = 0 FF FF FF FF FF FF FF
00000340: 00 FF FF FF FF FF FF FF = 10 FF FF FF FF FF FF FF
00000350: FF FF FF FF FF FF FF FF = FF FF FF FF FF FF FF FF
(00) CH:0 BK:0 => CH:0 CE:0
(08) CH:1 BK:0 => CH:1 CE:0
Exist Die
Bank 0 Ch0
Bank 0 Ch1
[vGDP_Nand_SwitchIF] L-TO-O30
[vGDP_Set_Nand_Timing],4
tx 20f rx 10014
rfc_pd_chan(0)->nphy_io_tx.config 0000020f
rfc_pd_chan(0)->nphy_io_rx.config 00010014
rfc_pd_chan(0)->nphy_io_delay.config 08080308
rfc_pd_chan(0)->nphy_delay_sel.config 00001008
rfc_pd_chan(0)->nifc_dqs_mask.config 000f0500
rfc_pd_chan(0)->nphy_actl_con.config 00000008
rfc_pd_chan(0)->nifc_cur_odt_ctl.config 00000000
rfc_pd_chan(1)->nphy_io_tx.config 0000020f
rfc_pd_chan(1)->nphy_io_rx.config 00010014
rfc_pd_chan(1)->nphy_io_delay.config 08080308
rfc_pd_chan(1)->nphy_delay_sel.config 00001008
rfc_pd_chan(1)->nifc_dqs_mask.config 000f0500
rfc_pd_chan(1)->nphy_actl_con.config 00000008
rfc_pd_chan(1)->nifc_cur_odt_ctl.config 00000000
rfc_pd_chan(2)->nphy_io_tx.config 0000020f
rfc_pd_chan(2)->nphy_io_rx.config 00010014
rfc_pd_chan(2)->nphy_io_delay.config 08080308
rfc_pd_chan(2)->nphy_delay_sel.config 00001008
rfc_pd_chan(2)->nifc_dqs_mask.config 000f0500
rfc_pd_chan(2)->nphy_actl_con.config 00000008
rfc_pd_chan(2)->nifc_cur_odt_ctl.config 00000000
rfc_pd_chan(3)->nphy_io_tx.config 0000020f
rfc_pd_chan(3)->nphy_io_rx.config 00010014
rfc_pd_chan(3)->nphy_io_delay.config 08080308
rfc_pd_chan(3)->nphy_delay_sel.config 00001008
rfc_pd_chan(3)->nifc_dqs_mask.config 000f0500
rfc_pd_chan(3)->nphy_actl_con.config 00000008
rfc_pd_chan(3)->nifc_cur_odt_ctl.config 00000000
nifc_timing_set.config 5555
nops_tmr_cnfg0.bits.nops_tmr_un0 682b
nops_tmr_cnfg0.bits.nops_tmr_un1 0a6b
nops_tmr_cnfg1.bits.nops_tmr_un2 010b
nops_tmr_cnfg1.bits.nops_tmr_un3 0000
nops_rty_cnfg0.bits.nops_rty_th0 00ff
nops_rty_cnfg0.bits.nops_rty_th1 00ff
nops_rty_cnfg0.bits.nops_rty_th2 00ff
nops_rty_cnfg0.bits.nops_rty_th3 00ff
Type 200
Pll 192097
[vGDP_Nand_SwitchIF] 1 28
=>ODT=0x6
qwSts = 0x6
qwSts = 0x6
=>DriverSetting=0x2
qwSts = 0x2
qwSts = 0x2
LDPC_MODE=0 SortingMode=0
SataS0=113
00000410: -- -- -- -- 03 00 00 00 = 00 00 00 00 03 00 00 00
00000420: 00 00 00 00 00 00 00 00 = 00 00 00 00 00 00 00 00
00000430: 00 00 00 00
Bank 0 Ch 0 LdrBlock 0
Bank 0 Ch 0 LdrBlock 1
Bank 0 Ch 1 LdrBlock 0
Bank 0 Ch 1 LdrBlock 1
<<<<< Loading Pattern Page >>>>>
LDPC Page block 0 bCh 0 page 3
LDPC Page block 0 bCh 0 page 4
Search Bank 0 Ch 0 BlockNo 0 page 5
E0021D80: 53 4F 52 54 00 01 00 00 = 99 00 2C 03 01 01 50 00
E0021D90: 00 00 00 39 37 39 30 33 = 31 31 39 34 31 31 39 00
Pattern Page block 0 bCh 0 page 5
Load Pattern Page Success (0)!!
RR Table
00 00 00 00 00 00 00 00
01 fb fd fc fb fe fd fe
bPatternPageFound=1
E0021D80: -- -- -- -- 00 01 00 00 = 99 00 2C 03 01 01 50 00
E0021D90: 00 00 00 39 37 39 30 33 = 31 31 39 34 31 31 39 00
E0021DA0: 00 00 00 00
gbLED_OP=0
boStopRDT=1
Stop RDT
:RDT task done.
-->[sata_ndt_crst]
<--[sata_ndt_crst]
-->[sata_ndt_xrst] 0
<--[sata_ndt_xrst]
-->[sata_ndt_xrst] 0
<--[sata_ndt_xrst]
-->[sata_ndt_xrst] 0
<--[sata_ndt_xrst]
-->[sata_ndt_xrst] 0
<--[sata_ndt_xrst] |
Всего записей: 599 | Зарегистр. 29-03-2016 | Отправлено: 22:19 05-09-2021 | Исправлено: exwein, 21:51 09-09-2021 |
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